![close this section of the library close this section of the library](/greenstone/web/images/bshelf.gif) | | Điện tử | (208) |
![](/greenstone/web/images/space.gif) | ![close this section of the library close this section of the library](/greenstone/web/images/bshelf.gif) | | Vi điện tử | (21) |
![](/greenstone/web/images/space.gif) |
![View the document View the document](/greenstone/web/images/itext.gif) | | A configurable AHB bus compatible with AMBA standard version 2.0
|
![View the document View the document](/greenstone/web/images/itext.gif) | | A design of all digital phase locked loop in submicron CMOS technology
|
![View the document View the document](/greenstone/web/images/itext.gif) | | A low-power asic implementation of OpenSPARC T1 processor using 90nm CMOS process
|
![View the document View the document](/greenstone/web/images/itext.gif) | | GSM900 - Communication Platform based on STORM-SoC FPGA Embedded
|
![View the document View the document](/greenstone/web/images/itext.gif) | | A soft error tolerant sram design in 130nm cmos technology
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Designing an embedded system based on FPGA for image recognition
|
![View the document View the document](/greenstone/web/images/itext.gif) | | A FPGA implementation of H.264/AVC video decoder
|
![View the document View the document](/greenstone/web/images/itext.gif) | | An experimental car navigation hardware based onhierarchical implicit shape modeling
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Research and design the PHY layer of an IEEE 802.11n 4x4 MIMO
|
![View the document View the document](/greenstone/web/images/itext.gif) | | VLSI architecture for chroma key effect in real - time
|
![View the document View the document](/greenstone/web/images/itext.gif) | | A study of high throughtput parallel AES - CCM for IEEE 802.11.ac
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Design of adaptive CORDIC-based discrete cosine transform on FPGA applied for image compression
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Clock data recovery using time domain approach
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Indirect compensation techiques for operational amplifiers
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Parameter extraction for BSIM3v3 model based on optimization algorithms
|
![View the document View the document](/greenstone/web/images/itext.gif) | | A flexible FPGA-based digital sound synthesizer
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Development of an advanced forward / inverse discrete cosine transform on FPGA
|
![View the document View the document](/greenstone/web/images/itext.gif) | | An implementation of power managment for ternary content addressable memory
|
![View the document View the document](/greenstone/web/images/itext.gif) | | FPGA design of speech compression by using discrete wavelet transform
|
![View the document View the document](/greenstone/web/images/itext.gif) | | FPGA implementation of a viterbi decoder for next generation broadband wireless access systems
|
![View the document View the document](/greenstone/web/images/itext.gif) | | Low power design for VLSI
|
|